The Next Generation of Microchip Manufacturing is Ten Years Away
Veldhoven, Thursday 8 October 2026
A new paper by ASML and Zeiss reveals next-generation technology could print 5-nanometre chip features in ten years, reusing existing light sources to shrink circuitry by a third.
Extending the EUV Roadmap
The publication of a joint peer-reviewed paper in the October 2026 issue of the Journal of Micro/Nanopatterning, Materials, and Metrology marks a pivotal moment for the global semiconductor roadmap [1][2]. Engineers from Veldhoven-based lithography giant ASML and its German optics partner Carl Zeiss SMT have outlined the technical viability of “Hyper-NA” Extreme Ultraviolet (EUV) lithography [1][2][3]. Featuring a numerical aperture (NA) of at least 0.75, this successor system represents a significant step beyond the current 0.55-NA High-NA EUV scanners [2][3]. The shift from 0.55 to 0.75 represents an increase in numerical aperture of 36.364 per cent, allowing chipmakers to push physical boundaries even further [GPT].
Ensuring European Supply Chain Resilience
This long-term planning provides crucial visibility for the European semiconductor ecosystem, which is increasingly focused on supply chain resilience and strategic autonomy [GPT]. By detailing a roadmap where commercial viability is projected for approximately ten years from now—around October 2036—the research allows deep-tech venture capitalists, academic institutions, and equipment suppliers to align their development cycles [1][3]. Crucially, Hyper-NA is designed to reuse ASML’s existing 13.5-nanometre EUV light sources, masks, and production infrastructure, while maintaining a footprint similar to the current double-decker bus-sized High-NA tools [1][3].
Engineering Challenges and Value Chain Integration
While the transition to Hyper-NA promises to print features as small as 5 nanometres—more than a third smaller than current High-NA capabilities—the technical challenges are formidable [1][3]. The paper details complex imaging parameters, including resist blur modelled as a Gaussian convolution and the delicate balance of polarised illumination [3]. While polarisation can mitigate contrast loss from vector effects, it incurs significant light energy loss, which increases Edge Placement Error (EPE) via shot noise [3]. To avoid these efficiency losses, Hyper-NA systems are primarily designed to support unpolarised illumination, requiring only minor modifications like adding linear polarisers for specific application needs [3].
Strategic Autonomy and Global Competition
Beyond lithography equipment, the broader semiconductor value chain is shifting focus toward holistic system integration [4]. As traditional transistor scaling faces physical limits, industry value is increasingly moving toward advanced packaging, AI infrastructure, and integrated photonics [4]. In Europe, organisations like PhotonDelta are driving the integration of co-packaged optics (CPO) to overcome bandwidth and power constraints [GPT][4]. This shift is critical as next-generation data centres and AI hardware demand system-level testing to manage multi-chiplet architectures and power consumption levels exceeding 1,000 W [4].
Sustaining Moore’s Law
The development of Hyper-NA technology reinforces Europe’s unique position in the global semiconductor landscape, anchored by ASML’s lithography monopoly and ASM International’s leadership in atomic layer deposition (ALD) [1][GPT]. By sustaining the roadmap for physical scaling, European players ensure that global giants—such as Intel, Samsung, SK Hynix, and TSMC—remain dependent on European toolmaking expertise [1]. This technological moat is essential for European strategic autonomy, providing leverage in a highly geopolitical industry where US startups like xLight and Substrate are actively pursuing alternative light sources and X-ray lithography [1].
A Decade of Innovation Ahead
Ultimately, the ten-year horizon for Hyper-NA EUV demonstrates that sustaining Moore’s Law requires a multi-decade commitment to fundamental research [4][GPT]. By establishing a clear optical path to 5-nanometre half-pitch resolution, ASML and Carl Zeiss SMT have reassured the market that the physical limits of silicon are still years away from being reached [1][3]. As the industry transitions from simple transistor scaling to complex, co-packaged optoelectronic systems, the integration of advanced lithography, chip design, and packaging will define the next era of global computing power [4][GPT].