ASML Expands Into Advanced Chip Packaging, Challenging Rival Besi

2026-10-16 semicon

Duiven, Friday 16 October 2026
Reports reveal lithography giant ASML is secretly developing hybrid bonding tools. This move into advanced chip packaging directly challenges market leader Besi, causing its share price to fall.

Market Reaction and SemiAnalysis Insights

Shares in Dutch chip packaging machinery specialist BE Semiconductor Industries (Besi) dropped by 3% to EUR 158.50 during midday trading on Friday, 16 October 2026, following reports that industry heavy-weight ASML is developing a competing hybrid bonding system [1]. Conversely, ASML’s share price rose by 1.1% to EUR 1,480 [1]. The market shift came after semiconductor research firm SemiAnalysis released details on 27 patent families filed by ASML between December 2022 and November 2024, indicating active development of a die-to-wafer (D2W) hybrid bonding tool intended for high-density advanced packaging [2][3][4].

Technical Architecture and Industrial Partnerships

According to technical analyses of patent filings such as WO2025201788A1 and WO2026098870A1, ASML’s proposed tool employs a track-based conveyance mechanism where individual dies are moved on dedicated holders past various process stations [2][4]. The integrated workflow executes surface cleaning, inspection, plasma activation, metrology, and topography detection on each die prior to final placement [2][4]. To support the physical assembly and precision movement of the apparatus, ASML is reportedly partnering with long-standing Dutch supply chain partners Prodrive Technologies and VDL ETG [2][3][4].

Addressing Bottlenecks in Advanced Logic Assembly

The current market for die-to-wafer hybrid bonding suffers from severe throughput constraints, with existing production setups bound to an upper limit of approximately one wafer per hour [2]. Commercial application of D2W bonding has so far been concentrated in advanced logic products—most notably AMD’s V-Cache series deployed since 2022 and TSMC’s System-on-Integrated-Chips (SoIC), which currently operates at a 6 µm pitch with roadmap targets aiming for 4.5 µm by 2029 [2][4]. ASML is expected to focus its tool on high-volume logic manufacturing, directly targeting core Besi customers such as TSMC and Intel Foundry, whilst high bandwidth memory (HBM) integration onto D2W bonding platforms is projected to be delayed until 2029 or beyond [2][3][6].

Strategic Integration and Competitive Dynamics

ASML’s move into back-end packaging builds upon a broader trend of vertical integration, following previous acquisitions of Cymer in 2013, High Yield Microdevices (HMI) in 2016, and Berliner Glas in 2020, as well as the release of its XT:260 i-line packaging scanner in the third quarter of 2025 [2]. By cross-referencing die coordinate positioning between lithography scanners and bonding tools, ASML aims to streamline alignment speed and overlay accuracy [2]. This competitive push comes as packaging gains crucial strategic weight globally; chip toolmakers in China are also investing in hybrid bonding technology as a primary avenue to sustain performance scaling amidst tight international export restrictions on front-end equipment [5].

Sources & Ecosystem Partners

Advanced Packaging Semiconductor Equipment