How Artificial Intelligence Is Solving the Stacking Dilemma in Advanced Microchips
Leuven, Saturday 14 November 2026
Imec and Matlantis have united to simulate microchip bonding at atomic scale, leveraging artificial intelligence to solve critical material hurdles in stacking chips for next-generation hardware.
Unlocking Next-Generation Packaging Through Atomistic AI
On 14 November 2026, Leuven-based nanoelectronics research hub imec signed a Joint Development Project agreement with Matlantis to pioneer machine-learning atomistic simulations for advanced semiconductor manufacturing [1]. Formally designated as SIMPL (Simulations with Machine-Learning Potentials), the collaborative venture targets one of the most stubborn bottlenecks in 3D integrated circuit assembly: evaluating the atomic adhesion of hybrid bonding [1]. Led by imec Fellow Geoffrey Pourtois and Matlantis Chief Executive Officer Daisuke Okanohara, the research evaluates Matlantis’s Preferred Potential (PFP) universal machine-learning interatomic potential on nanoelectronic materials [1]. The initiative focuses directly on simulating the boundary interfaces where amorphous dielectrics meet polycrystalline metals, creating a predictive framework designed to bypass empirical trial-and-error in advanced packaging [1].
The Economics of Stacking and the Interconnect Bottleneck
As traditional 2D transistor scaling faces compounding physical constraints and rising fabrication costs, the semiconductor industry has shifted focus toward vertical heterogenous integration [2][GPT]. High-performance computing workloads—particularly artificial intelligence models—face severe operational penalties because transferring data between discrete memory and logic units often consumes considerably more energy and bandwidth than the underlying compute operations [2]. Hybrid bonding circumvents this penalty by joining chiplets directly through seamless copper-to-copper and dielectric-to-dielectric connections, eliminating conventional intermediate solder micro-bumps entirely [2]. This architecture enables significantly higher interconnect density across much shorter spatial distances, driving higher input/output throughput while dampening thermal and energetic dissipation [2].
Overcoming the Quantum Mechanics Computational Barrier
The physical reliability of hybrid bonding depends entirely on atomic-level bonding dynamics, where structural stability across amorphous and polycrystalline layers dictates whether an interface will delaminate under operational stresses [1][2]. Historically, simulating these macroscopic-scale interface boundaries has proven computationally intractable using standard density functional theory (DFT), which struggles with systems that are simultaneously disordered and too expansive for classical ab initio calculations [2]. Susumu Ohno, Executive Vice President of Sales & Business Development at Matlantis, highlighted that machine-learning interatomic potentials bridge this gap by enabling rapid atomic-scale exploration across multi-element interfaces that are otherwise too large and disordered for traditional DFT methods [2]. By deploying AI-driven simulation platforms, the SIMPL alliance accelerates experimental throughput, transforming how chip designers predict mechanical durability [1][2].
Strengthening European Strategic Autonomy Across the Value Chain
This research alliance in Leuven holds broader macroeconomic significance for Europe’s technological autonomy and supply chain resilience [GPT]. Leading equipment manufacturers such as ASML and ASM International are progressively aligning their lithography, atomic layer deposition, and wafer-handling roadmaps with advanced 3D stacking requirements [GPT]. Concurrently, European ecosystems including the Netherlands-based PhotonDelta initiative are driving integrated photonics to overcome copper interconnect barriers in inter-chip communication [GPT]. By anchoring hybrid bonding materials modeling within imec’s European R&D hub, the partnership reinforces the regional design pipeline, empowering domestic and global foundries to integrate complex chiplet architectures while hedging against concentrated geopolitical supply risks [1][GPT].