Semiconductor Leaders Unite to Redesign Microchip Manufacturing Templates

2026-09-09 semicon

Veldhoven, Wednesday 9 September 2026
ASML, TSMC, Samsung, and Intel have partnered to develop larger 12-inch photomasks by 2031, eliminating manufacturing limits to boost the production of next-generation AI microchips.

Overcoming the High-NA Physical Bottleneck

On 8 September 2026, Veldhoven-based lithography giant ASML and Taiwan Semiconductor Manufacturing Company (TSMC) announced a landmark joint industry initiative to transition from current 6-inch square photomasks to larger 12-inch by 6-inch (approximately 152.4 mm by 304.8 mm) formats [1][4]. Photomasks act as the vital stencils used to print complex circuit designs onto silicon wafers during the chipmaking process [7]. This transition addresses a critical physical limitation in ASML’s next-generation High-NA extreme ultraviolet (EUV) lithography systems, such as the TWINSCAN EXE:5000 and EXE:5200B [1][6]. While these advanced systems achieve an exceptional eight-nanometre resolution—allowing structures 1.7 times smaller than legacy NXE low-NA machines—they also reduce the exposure field area by half [1][6]. Specifically, the exposure field shrinks from the low-NA standard of 858 mm² to just 429 mm², representing a reduction of 50% [4].

Restoring Single-Step Exposure Efficiency

This halved exposure field forces chipmakers to use a process called “stitching,” where large semiconductor designs—such as high-performance artificial intelligence (AI) graphics processing units (GPUs)—must be printed in two separate parts and then meticulously aligned [4][6]. By introducing the larger 12-inch format, which has an area of 72 square inches, the industry aims to restore the full 858 mm² single-step exposure capability [4]. ASML projects that this transition to larger photomasks will boost manufacturing productivity by approximately 40% [6]. It combines the high throughput of High-NA tools with the larger single-exposure print area, significantly lowering chipmaking costs per unit [4][7].

A Phased Roadmap for Global Fab Integration

The industry initiative, which has also been joined by Samsung Electronics and Intel, outlines a clear timeline to scale this technology [1][4]. The collaborative roadmap targets the establishment of a 12-inch mask pilot line by 2031, with full readiness for advanced-node mass production scheduled for 2033 [1][4]. Despite the long-term shift, chipmakers are already forging ahead with immediate High-NA deployment using existing 6-inch masks [5]. Intel, which has collaborated with ASML on the larger photomask format for over three years, is already utilising High-NA lithography in production for select layers of its Panther Lake processors [1][5]. By using stitching techniques and Process Design Kits (PDKs) developed by Intel Foundry, designers can build complex AI chips today without waiting for the larger mask standards to mature [5].

Diverging Timelines Among Chip Giants

Other global chipmaking giants are following distinct integration timelines. Samsung has confirmed plans to deploy High-NA technology for high-volume DRAM memory production by 2028, making it the first memory manufacturer to do so, before expanding to 1-nanometer-class logic chip production around 2030 [1][4][6]. Meanwhile, TSMC plans to commence high-volume production using High-NA tools for advanced nodes in 2030, potentially integrating them into its A10 (1nm-class) process, prior to the adoption of the larger mask format [1][4]. This phased approach ensures that the industry can immediately leverage the precision of High-NA systems while progressively building the ecosystem—comprising mask makers, electronic design automation (EDA) partners, and material suppliers—needed for the 12-inch transition [4][5].

Strengthening the European Semiconductor Value Chain

This technological leap reinforces the strategic importance of the European semiconductor ecosystem, particularly the Benelux deep-tech cluster [GPT]. ASML’s lithography systems are the cornerstone of global chip manufacturing, but they rely on a highly integrated European supply chain that includes equipment manufacturers like ASM International and research hubs focusing on integrated photonics, such as PhotonDelta [GPT]. By pioneering these new standards, Europe secures its position at the absolute forefront of global semiconductor equipment manufacturing and deep-tech innovation [GPT]. This collective advancement is vital for European strategic autonomy, ensuring that the region remains an indispensable anchor in the global technology supply chain amid rising geopolitical tensions and rising demand for advanced AI hardware [GPT].

Economic Implications and Market Dynamics

The transition to High-NA EUV represents a massive financial commitment for global chipmakers. Each High-NA machine represents a colossus of engineering, carrying an estimated price tag of approximately €200 million to $400 million [4][7]. Despite these high capital requirements, strong demand for next-generation AI processors has driven key market players to commit to the technology [7]. ASML, which derives 74.9% of its revenue from lithography equipment sales and 25.1% from services, is carefully managing its manufacturing footprint to meet this demand [3]. As of 2026, ASML’s global revenue distribution remains highly diversified, with China accounting for 29.1%, Taiwan for 25.5%, South Korea for 25%, and the United States for 12.5% [3]. To support this accelerating transition, ASML has announced plans to expand its total EUV manufacturing capacity by approximately 30% in 2027, giving investors greater visibility into the company’s long-term growth trajectory [7].

Sources & Ecosystem Partners

Semiconductor Lithography High-NA EUV